1. Field of the Invention
The invention relates to a LVDS and TMDS dual function device, and in particular to a LVDS and TMDS dualfunction device with a set of pins outputting signals using serializers coupled to both internal LVDS and TMDS signals.
2. Description of the Related Art
LVDS and TMDS are two major interfaces for flat panel display devices. A graphic device driving flat panel display devices normally includes both interfaces, and in some designs, both interfaces are implemented through the same group of pins.
FIG. 1 is a block diagram of a conventional LVDS/TMDS dual function transmitter 10, including twenty-eight bits of LVDS signals (i.e. RED (0:7), GREEN (0:7), BLUE (0:7), HSYNC, VSYNC, DE and D23Y(not shown in FIG. 1) signals), an encoder 12 encoding the LVDS signals to thirty bits of TMDS signals, an LVDS serializer 11, a TMDS serializer 13, a LVDS driver 14, and a TMDS driver 15.
In LVDS mode, the transmitter directs the twenty-eight bits of LVDS signals, to four output channels of the LVDS serializing device 11 with 7:1 serializers. In TMDS mode, the transmitter first directs the twenty-eight bits of LVDS signals to encoder 12, then 30 encoded signals are separated to 3 data streams (10-bit) for the three output channels of the TMDS serializing device 13 with 10:1 serializer.
Finally, the LVDS driver 14 and TMDS driver 15 are coupled together for each channel (except channel 0), such that data is output from the same terminal like YTX0, YTX1, YTX2, YTX3, and YTXC (clock channel). The channel YTX0 is only enabled for the LVDS mode.
The LVDS serializer and TMDS serializer utilize parallel-to-serial devices to serialize data. FIG. 2 is a block diagram of an LVDS serializer channel 200 including seven cells 201 to 207. Each cell receives a data signal and two phase signals. In this embodiment, 14 phase signals deliver 14 phases respectively per clock period, wherein each two phases is delivered to a cell outputting a portion of a serial bit stream. A 7-bit data stream per clock period is then formed in the LVDS channel. FIGS. 3A and 3B illustrate a block diagram of a TMDS serializer channel 300 including ten cells 301˜310. Each cell receives a data signal and a phase signal. In this embodiment, 10 phase signals deliver 10 phases respectively per clock period, wherein each phase is delivered to a cell outputting a portion of a serial bit stream. A 10-bit data stream by per clock period is then formed in the TMDS channel.
Larger layout area is occupied when combining LVDS and TMDS driving devices directly, since each occupies its serialization path respectively. When LVDS and TMDS driving devices are implemented separately, flexibility may be compromised.